A TCP type semiconductor apparatus (hereinafter, referred to as “TCP”) and a COF type semiconductor apparatus (hereinafter, referred to as “COF”) have been widely known as a semiconductor apparatus obtained by bonding and mounting a semiconductor element on an insulating flexible wire substrate. The TCP is obtained by installing (mounting), by using the TCP (Tape Carrier Package) method, a semiconductor element on an insulating tape that is a base material of the flexible wire substrate. The COF is obtained by installing (mounting), by using the COF (Chip On Film) method, a semiconductor element on such an insulating tape.
Difference between the TCP and the COF is as follows. The TCP has an aperture portion (through hole) that is termed a “device hole” and that is provided beforehand in the aforementioned semiconductor element installation portion of the insulating tape, and the semiconductor element is bonded with front ends of wire patterns protruding, in a cantilever manner, in the aperture portion. On the other hand, the COF does not have such an aperture portion (device hole) for mounting a semiconductor element, and the semiconductor element is bonded and mounted on a surface of the insulating tape.
To accommodate to an intended use of the COF, the insulating tape used in the COF is a freely foldable thin film insulating tape. Provided on the surface of the insulating tape are wires of wire patterns, and the wires are electrically connected to relevant terminals of the semiconductor element. The insulating tape (the flexible wire substrate) has an external conductive connector portion that is connected to external electronic devices such as a liquid crystal panel and a print substrate. Note that, for securing insulation, a solder resist is applied to a pattern exposed portion excluding (i) the connection region where the wire patterns are connected with the semiconductor element, and (ii) the external conductive connector portion.
Presently required is realization of such a COF that deals with a larger number of pins, and that is smaller and thinner in shape. In order to satisfy such demands at the same time, the external conductive connector portion, and the connection portion connecting to the semiconductor element are each required to have fine pitches, and the tape carrier (insulating tape), the wire pattern, and the like are each required to be thinner. Further, for reduction of the pitch of the inner leads (the connection portion to the semiconductor element) of the wire patterns, each inner lead is required to be narrower and thinner.
There is an effective method for manufacturing a COF that deals with a larger number of pins and that allows acquirements of such a fine pitch, a narrow pitch, an edge touch, and the like. Examples of such a method include: (i) a connecting-sealing method termed the MMB (Micro Bump Bonding); and (ii) a connecting-sealing method (hereinafter, referred to as NCP etc.) termed the NCP (Non Conductive Paste) or APC (Anisotropic Conductive Paste), each of which has drawn attention recently. (For example, see Japanese Laid-Open Patent Publication Tokukaisho 60-262430/1985 (published on Dec. 25, 1985; corresponding to Japanese Examined Patent Publication Tokukouhei 2-7180 published on Feb. 15, 1990; hereinafter, referred to as “Patent document 1”) and Japanese Laid-Open Patent Publication Tokukaisho 63-151033/1988 (published on Jun. 23, 1988; corresponding to Japanese Examined Patent Publication Tokukouhei 7-77227 published on Aug. 16, 1995; hereinafter, referred to as “Patent document 2”)).
Each of the connecting-sealing methods such as the NCP etc., is a method for connecting protruding electrodes (connecting terminals) of a semiconductor element to respective wire patterns (connecting terminals) of a flexible wire substrate, and for sealing the protruding electrode and the wire pattern with a photo-curable or thermo-curable resin, each of which serves as an insulating resin and is provided beforehand between the semiconductor element and the flexible wire substrate by applying the insulating resin to a surface of an insulating tape.
For example, Patent document 1 shows an example using the MBB as follows. That is, a photo-curable or thermo-curable resin is applied to those wire patterns of the wire substrate which correspond to the protruding electrodes of the semiconductor element, respectively. The protruding electrodes and the wire patterns are aligned with each other, and the insulating resin between the protruding electrodes and the wire patterns is pushed out by applied pressure, so that electric conduction between the protruding electrode and the wire pattern is attained only by way of the pressure. The insulating resin thus pushed out extends to a periphery of the semiconductor element, and thereafter is cured by light or heat so as to fix the semiconductor element to the wire substrate and electrically connect the semiconductor element to the wire substrate.
Meanwhile, Patent document 2 shows another example using the MBB as follows. That is, a thermo-curable resin is applied to those wire patterns of the wire substrate which correspond to the respective protruding electrodes of the semiconductor elements. The semiconductor element is combined, by applying pressure to the semiconductor element with the use of a pulse heating tool, with the wire substrate such that the protruding electrodes are aligned with the wire patterns. The thermo-curable resin on the wire patterns is pushed out by the applied pressure. Thereafter, under application of pressure, an electric current is applied to the pulse heating tool so that the thermo-curable resin is heated and cured. This fixes the semiconductor element on the wire substrate, and electrically connects the protruding electrodes with the wire patterns.
However, neither Patent documents 1 nor 2 particularly discloses a method for applying the insulating resin, and a method for aligning the protruding electrode and the wire patterns.
However, in each of the above connecting-sealing methods such as the NCP etc., the semiconductor element is bonded by way of applying pressure after (i) the application of the insulating resin to the wire patterns of the insulating tape and (ii) the alignment of the protruding electrodes with the wire patterns. Therefore, for the alignment of the protruding electrodes and the wire patterns, an alignment mark pattern (hereinafter, referred to as “alignment mark”) is required to be provided so as to prevent a positioning (alignment) error thereof and exposure of the wire patterns.
By the way, it is difficult to control a resin region with a conventional technique such as Au (gold)-Sn (tin) eutectic bonding, by which an insulating resin termed “under fill” is poured into a space between a semiconductor element and a wire substrate after connecting protruding electrodes and wire patterns. Specifically, when an alignment mark is provided within an aperture portion of a solder resist, the alignment mark is partially exposed, and is undistinguishable from exposure of the wire patterns. For this reason, the alignment mark is provided outside the aperture portion of the solder resist.
Therefore, for prevention of such exposure of the wire pattern also when using the connecting-sealing method such as the NCP etc., the alignment mark is required to be provided outside the application region of the insulating resin, in other words, outside of the aperture portion of the solder resist, the alignment mark being used for alignment upon connecting the protruding electrodes and the wire patterns.
In fact, an alignment mark partially covered with an insulating resin cannot be detected when the alignment mark is partially covered with an insulating resin, so that the alignment mark is provided, outside the aperture portion of the solder resist, away from the solder resist as distant as possible.
Here, the following explains a method for manufacturing a COF by using the connecting-sealing method such as the NCP etc., in other words, a method for installing a semiconductor element on a wire substrate, with reference to FIG. 13, FIG. 14, FIG. 15, and FIG. 16(a) through FIG. 16(e).
FIG. 13 is a plan view schematically illustrating a structure of a semiconductor apparatus in which alignment marks are provided outside an aperture portion of a solder resist. FIG. 14 is a plan view schematically illustrating a semiconductor element installation region in the semiconductor apparatus shown in FIG. 13. Note that, for ease of explanation, FIG. 14 indicates the semiconductor element by a chain double-dashed line, and indicates, by a broken line surrounding the chain double-dashed line, an installation site region (cover region) where the insulating resin is installed. In other words, the region surrounded by the chain double-dashed line in FIG. 14 indicates an overlap region overlapping with the semiconductor element. Whereas, the region surrounded by the broken line surrounding the region surrounded by the chain double-dashed line indicates the installation site region of the insulating resin, in other words, the installation region where the semiconductor element is installed by means of the insulating resin.
FIG. 15(a) through FIG. 15(e) and FIG. 16(a) through FIG. 16(e) are cross sectional views each illustrating a major part of the semiconductor apparatus taken along a line B-B′ in FIG. 14. FIG. 15(a) through FIG. 15(e) illustrate steps of installing the semiconductor element on a wire substrate in Patent document 1, whereas FIG. 16(a) through FIG. 16(e) illustrate steps of installing the semiconductor element on a wire substrate in Patent document 2.
As shown in FIG. 13, FIG. 14, and FIG. 15(a), in cases where the semiconductor element is installed on the wire substrate in accordance with the method described in Patent document 1 by using the alignment marks, each of alignment marks 1 is provided, for alignment upon connecting protruding electrodes 13 of the semiconductor element 12 with connecting terminals 2a of wire patterns 2, outside an aperture portion 4a of the solder resist 3. The aperture portion 4a is so formed as to surround the connection-overlap portion of the semiconductor element 12 in a tape carrier 10 (insulating tape) used in a wire substrate 201.
Note that the semiconductor apparatus shown in FIG. 13, FIG. 14, and FIG. 15(a) through FIG. 15(e) has aperture portions 4b, which are parts of an aperture portion 4′ of the solder resist 3 and which are provided in respective installation portions of the alignment marks 1.
As shown in FIG. 14 and FIG. 15(b), a photo-curable or thermo-curable insulating resin 11 is so applied as to cover each connecting terminal 2a. Next, alignment of protruding electrodes 13 with the connecting terminals 2a is carried out after carrying out (i) detection of each alignment mark 1 as indicated by arrows 14 in FIG. 15(c), and (ii) detection of each of alignment marks 5 (see FIG. 14), provided on an active face of the semiconductor element 12, as indicated by arrows 15. Thereafter, pressure is applied as indicated by arrows 17 in FIG. 15(d). This pushes out the insulating resin 11 provided between the protruding electrode 13 and the connecting terminal 2a, and the insulating resin 11 thus pushed out extends to a periphery of the semiconductor element 12, and is cured by light irradiation or heat application as indicated by arrows 18 in FIG. 15(e). With this, the semiconductor element 12 is fixed to the wire substrate 201.
Likewise, as shown in FIG. 13, FIG. 14, and FIG. 16(a), in cases where the semiconductor element is installed on the wire substrate in accordance with the method described in Patent document 2 by using the alignment marks, each of alignment marks 1 is provided, for alignment upon connecting a protruding electrode 13 of the semiconductor element 12 with connecting terminals 2a of wire patterns 2, outside an aperture portion 4a of the solder resist 3. The aperture portion 4a is so formed as to surround the connection-overlap portion of the semiconductor element 12 on a tape carrier 10 (insulating tape) used for a wire substrate 201.
Note that, also in this case, the semiconductor apparatus has aperture portions 4b, which are parts of an aperture portion 4′ of the solder resist 3 and which are provided in respective installation portions of the alignment marks 1.
As shown in FIG. 14 and FIG. 16(b), a thermo-curable insulating resin 11 is so applied as to cover each connecting terminal 2a. Next, detection of each alignment mark 1 is carried out as indicated by arrows 14 in FIG. 16(c), and detection of the alignment mark 5 (see FIG. 14) provided on the active face of the semiconductor element is carried out as indicated by arrows 15. Then, pressure is applied to the semiconductor element 12 with the use of a pulse heating tool (not shown) in such a manner that, to cause the protruding electrodes 13 to be aligned with and in contact with the connecting terminals 2a, the insulating resin 11 on the connecting terminals 2a is pushed out, by the applied pressure, to a periphery of the insulating resin 11, as indicated by arrows 17 in FIG. 16(d). Thereafter, under application of pressure as indicated by arrows 19 in FIG. 16(e), an electric current is applied to the pulse heating tool so as to heat and cure the insulating resin 11. This fixes the semiconductor element 12 to the wire substrate 201, and electrically connects each protruding electrode 13 and the connecting terminal 2a. 
However, as described above, each wire pattern 2 is required to be provided away from such an alignment mark 1 provided outside the aperture portion 4a of the solder resist 3, i.e., outside the application region of the insulating resin 11 in Patent documents 1 and 2. This causes an increase in an outer size of a semiconductor apparatus obtained by employing the COF method.
Further, when the insulating resin 11 is applied beyond the aperture portion 4a for prevention of exposure of the wire pattern 2 within the aperture portion 4a, each alignment mark 1 is possibly covered partially with the insulating resin 11. Such an alignment mark 1 partially covered with the insulating resin 11 deteriorates detection accuracy of the alignment mark 1 to such a degree that the alignment mark 1 cannot be accurately detected. This deteriorates the connection position accuracy of the protruding electrodes 13 of the semiconductor element 12 and the connecting terminals 2a of the wire patterns 2.
What is required to prevent such a positioning (alignment) error between the protruding electrodes 13 and the connecting terminals 2a is that: (i) the insulating resin 11 is applied, away from the formation region (aperture portion 4b) of the alignment mark 1 as distant as possible, in order not to spread over the alignment mark 1 as shown in FIG. 14; or (ii) the alignment mark 1 is provided as distant as possible from the aperture portion 4a of the solder resist 3. However, when the alignment mark 1 is provided distantly away from the aperture portion 4a of the solder resist 3, the connection position accuracy is deteriorated and outer size of the semiconductor apparatus becomes large. Meanwhile, when the insulating resin 11 is applied so as not to spread over the alignment mark 1, the wire pattern 2 tends to be exposed within the aperture portion 4a as shown in FIG. 14.